| CPC H01L 21/0337 (2013.01) [H01L 21/0276 (2013.01); H01L 21/0332 (2013.01); H01L 21/31116 (2013.01); H01L 21/31122 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H10B 12/01 (2023.02)] | 17 Claims |

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1. A preparation method for a semiconductor structure, comprising:
providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate;
patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer;
forming spacers with vertical sidewall morphology on sidewalls of the first mask layer;
removing the first mask layer;
forming a filling layer on the bottom mask layer, the filling layer filling a gap between two adjacent ones of the spacers and covering the spacers;
planarizing the filling layer such that an upper surface of the filling layer is flush with upper surfaces of the spacers,
wherein there is a high etching selectivity ratio of a material of the spacers to a material of the filling layer;
removing the spacers;
forming a second mask layer on the filling layer;
etching the second mask layer to form a second pattern, the second pattern exposing parts of the filling layer; and
patterning the filling layer with the second mask layer as a mask to form a filling layer mask.
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