US 12,340,870 B2
Method for forming a semiconductor device pillar with source, channel, and drain
Yiming Zhu, Hefei (CN); and Erxuan Ping, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 14, 2022, as Appl. No. 17/575,806.
Application 17/575,806 is a continuation of application No. PCT/CN2021/086467, filed on Apr. 12, 2021.
Claims priority of application No. 202010343514.2 (CN), filed on Apr. 27, 2020.
Prior Publication US 2022/0139431 A1, May 5, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/18 (2006.01); H10B 12/00 (2023.01); H10B 51/40 (2023.01); H10B 53/40 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC G11C 7/18 (2013.01) [H10B 12/482 (2023.02); H10B 51/40 (2023.02); H10B 53/40 (2023.02); H10B 61/20 (2023.02); H10B 63/34 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing a substrate, wherein a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate;
patterning the active layer and the sacrificial layer to form grooves which divide the active layer and the sacrificial layer into a plurality of active areas;
filling the grooves to form a first isolation layer surrounding the active areas;
patterning the active layer in the active areas to form a plurality of active lines which are arranged in parallel and extend along a first direction, wherein at least one of a side wall or an end portion of each active line is connected to the first isolation layer;
removing the sacrificial layer via openings between adjacent active lines to form gaps between bottoms of the active lines and the substrate;
forming bit lines in the gaps;
patterning the active lines to form a plurality of active pillars which are arranged in array along the first direction and a second direction after the bit lines are formed;
forming semiconductor pillars on tops of the active pillars;
forming a first doped region in each active pillar;
forming, in each semiconductor pillar, a channel region and a second doped region above the channel region; and
forming a gate structure surrounding the channel region.