US 12,340,869 B2
Low power wake up for memory
Sanjeev Kumar Jain, Kanata (CA); and Atul Katoch, Kanata (CA)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 22, 2023, as Appl. No. 18/518,157.
Application 18/518,157 is a continuation of application No. 17/714,754, filed on Apr. 6, 2022, granted, now 11,854,587.
Claims priority of provisional application 63/285,883, filed on Dec. 3, 2021.
Prior Publication US 2024/0087618 A1, Mar. 14, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 5/14 (2006.01)
CPC G11C 7/1063 (2013.01) [G11C 5/14 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 2207/2227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
an output driver coupled to a memory cell storing data;
wherein the output driver is configured to generate an output signal having a predetermined voltage irrespective of the stored data, in response to a sleep tracking signal indicating that the memory cell is in a sleep state; and
wherein the sleep tracking signal is delayed from a sleep control signal and configured to causing the memory cell to operate in the sleep state or the operational state.