US 12,340,867 B2
Memory device including on-die-termination circuit
Eun-Ji Kim, Suwon-si (KR); Jung-June Park, Seoul (KR); Jeong-Don Ihm, Seongnam-si (KR); Byung-Hoon Jeong, Hwaseong-si (KR); and Young-Don Choi, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 25, 2023, as Appl. No. 18/201,853.
Application 18/201,853 is a continuation of application No. 17/182,357, filed on Feb. 23, 2021, granted, now 11,705,166.
Application 17/182,357 is a continuation of application No. 16/875,163, filed on May 15, 2020, granted, now 10,964,360, issued on Mar. 30, 2021.
Application 16/875,163 is a continuation of application No. 16/058,709, filed on Aug. 8, 2018, granted, now 10,672,436, issued on Jun. 2, 2020.
Claims priority of application No. 10-2017-0146179 (KR), filed on Nov. 3, 2017.
Prior Publication US 2023/0298639 A1, Sep. 21, 2023
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 2207/105 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first memory including a first on-die Termination (ODT) circuit;
a second memory including a second ODT circuit;
a third memory including a third ODT circuit;
a first chip enable signal pin that is commonly connected to the first memory and the second memory, and receives a first chip enable signal;
a second chip enable signal pin that is connected to the third memory, and receives a second chip enable signal; and
an input/output pin that is commonly connected to the first memory, the second memory, and the third memory, and receives an address,
wherein in response to an ODT signal being enabled, and the first chip enable signal being disabled, the first ODT circuit is configured to provide a first ODT resistor that terminates a signal received by the first memory, and
in response to the ODT signal being enabled, the first chip enable signal being enabled, and the address selecting the second memory, the first ODT circuit is configured to provide a second ODT resistor that terminates the signal received by the first memory.