US 12,340,866 B2
Shift register unit, driving method thereof, and device
Guangliang Shang, Beijing (CN); Xinshe Yin, Beijing (CN); Qian Yang, Beijing (CN); Libin Liu, Beijing (CN); Shiming Shi, Beijing (CN); and Dawei Wang, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Mar. 15, 2024, as Appl. No. 18/606,074.
Application 18/606,074 is a continuation of application No. 17/828,425, filed on May 31, 2022, granted, now 11,961,582.
Application 17/828,425 is a continuation of application No. 16/767,755, granted, now 11,380,374, previously published as PCT/CN2019/094451, filed on Jul. 2, 2019.
Prior Publication US 2024/0221794 A1, Jul. 4, 2024
Int. Cl. G09G 5/00 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); G11C 7/10 (2006.01); G11C 7/14 (2006.01); G11C 7/22 (2006.01); G11C 19/28 (2006.01)
CPC G11C 7/1036 (2013.01) [G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 7/14 (2013.01); G11C 7/222 (2013.01); G11C 19/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
an input circuit configured to provide a signal of an input signal terminal to a first node in response to a signal of a first clock signal terminal; and provide a signal of a first reference signal terminal to a second node in response to the signal of the first clock signal terminal;
a node control circuit, connected with the first node, the second node and the first clock signal terminal respectively; wherein the node control circuit is configured to provide the signal of the first clock signal terminal to the second node in response to a signal of the first node;
a first control output circuit configured to control a signal of a third node according to a signal of a first control signal terminal and a signal of the second node;
a second control output circuit configured to provide a signal of a second reference signal terminal to a signal output terminal according to a signal of a second control signal terminal and the signal of the second node; and
an output circuit configured to provide a signal to the signal output terminal according to the signal of the first node;
wherein the output circuit comprises an eleventh transistor, a twelfth transistor, and a thirteenth transistor; a first electrode of the eleventh transistor is coupled to the input circuit, and a second electrode of the eleventh transistor is coupled to a gate electrode of the thirteenth transistor; a first electrode of the twelfth transistor is coupled to the input circuit, and a second electrode of the twelfth transistor is coupled to the gate electrode of the thirteenth transistor;
wherein the eleventh transistor and the twelfth transistor are configured to provide a signal output from the input circuit to the gate electrode of the thirteenth transistor when the input circuit is conductive.