US 12,340,864 B2
Interface level-shifter dual-rail memory architecture
Harold Pilo, Underhill, VT (US); Shishir Kumar, Noida (IN); Anurag Garg, Cupertino, CA (US); Peter Lee, Pleasanton, CA (US); and John Edward Barth, Williston, VT (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 8, 2023, as Appl. No. 18/107,450.
Claims priority of provisional application 63/309,409, filed on Feb. 11, 2022.
Prior Publication US 2023/0260555 A1, Aug. 17, 2023
Int. Cl. G11C 5/14 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/10 (2006.01); G11C 29/10 (2006.01)
CPC G11C 5/148 (2013.01) [G11C 7/06 (2013.01); G11C 7/1096 (2013.01); G11C 7/222 (2013.01); G11C 8/10 (2013.01); G11C 29/10 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
clock signal generation circuitry configured to receive a first clock signal and an isolation signal, and generate a second clock signal based on the first clock signal and the isolation signal, the isolation signal corresponds to a power state of a power supply associated with the first clock signal, wherein the second clock signal maintains a first voltage value based on the isolation signal indicating a power off state of the power supply and that the first clock signal is stopped, and the second clock signal includes transitions between the first voltage value and a second voltage value based on the isolation signal indicating a power on state of the power supply; and
first integrated level shifter and latch circuitry configured to:
receive an input signal in a first power supply domain;
latch a value the input signal based on the second clock signal, wherein the first integrated level shifter maintains the latch of the value based on the second clock signal maintaining the first voltage value and the isolation signal indicating the power off state of the power supply and that the first clock signal is stopped; and
output, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.