US 12,340,863 B2
Stacked memory chip solution with reduced package inputs/outputs (I/Os)
Chong J. Zhao, West Linn, OR (US); Shigeki Tomishima, Portland, OR (US); Kuljit S. Bains, Olympia, WA (US); James A. McCall, Portland, OR (US); and Dimitrios Ziakas, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 9, 2021, as Appl. No. 17/372,298.
Prior Publication US 2021/0335393 A1, Oct. 28, 2021
Int. Cl. G11C 16/04 (2006.01); G11C 5/06 (2006.01)
CPC G11C 5/066 (2013.01) 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a logic chip upon which a stack of memory chips is to be placed, the stack of memory chips and the logic chip to be placed within a same package, wherein multiple memory chips of the stack of memory chips are divided into fractions;
multiple internal channels within the same package that emanate from the logic chip to be coupled to respective ones of the fractions; and
the logic chip comprising:
a multiplexer, the multiplexer to multiplex a single input/output (I/O) channel of the same package to the multiple internal channels, and
a second multiplexer, the second multiplexer to multiplex other multiple internal channels within the same package coupled to other ones of the fractions to another single I/O channel of the same package.