US 12,340,859 B2
Hybrid memory system with increased bandwidth
Jungwon Suh, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 20, 2024, as Appl. No. 18/668,593.
Application 18/668,593 is a continuation of application No. 17/658,846, filed on Apr. 12, 2022, granted, now 12,073,901.
Claims priority of provisional application 63/284,439, filed on Nov. 30, 2021.
Prior Publication US 2024/0304271 A1, Sep. 12, 2024
Int. Cl. G11C 29/42 (2006.01); G11C 7/10 (2006.01); G11C 8/18 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/1048 (2013.01); G11C 7/1063 (2013.01); G11C 8/18 (2013.01); G11C 29/1201 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory device having a plurality of memory banks, comprising:
a first pseudo-channel coupled to a first group of the plurality of memory banks, comprising:
a first group of data conductors configured to receive or send data in the first pseudo-channel, wherein data signals and data mask signals are combined to encode a byte across a plurality of data conductors of the first group of data conductors;
a first differential write clock conductor pair configured to receive first clock signals for reading or writing the data in the first pseudo-channel; and
a first differential read strobe clock (RDQS) conductor pair configured to send first strobe signals during a read operation for the data in the first pseudo-channel; and
a second pseudo-channel coupled to a second group of the plurality of memory banks, comprising:
a second group of data conductors configured to receive or send data in the second pseudo-channel;
a second differential write clock conductor pair configured to receive second clock signals for reading or writing the data in the second pseudo-channel; and
a second differential RDQS conductor pair configured to send second strobe signals during a read operation for the data in the second pseudo-channel.