| CPC G11C 19/287 (2013.01) [G09G 3/3225 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01)] | 17 Claims |
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1. A shift register unit, comprising:
an input circuit configured to provide an input signal to a first node in response to a first clock signal;
a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal;
a first control circuit configured to provide the second clock signal to the second node in response to a first control signal;
an output circuit configured to provide a third clock signal to a drive output terminal in response to a signal of the first node, and provide a second reference signal to the drive output terminal in response to a signal of the second node;
wherein a duration of an active level of the first control signal is longer than a duration of an active level of a signal of the drive output terminal;
wherein the input circuit comprises a second transistor;
a control electrode of the second transistor is configured to receive the first clock signal, a first electrode of the second transistor is configured to receive the input signal, and a second electrode of the second transistor is coupled to the first node;
wherein the input circuit further comprises a third transistor; and the second electrode of the second transistor is coupled to the first node through the third transistor;
a control electrode of the third transistor is configured to receive the first clock signal, a first electrode of the third transistor is coupled to the second electrode of the second transistor, and a second electrode of the third transistor is coupled to the first node;
wherein the shift register unit further comprises: a first noise reduction circuit;
the first noise reduction circuit is configured to provide the third clock signal to the first electrode of the third transistor in response to the signal of the drive output terminal.
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