US 12,340,849 B2
Memory device for detecting fail cell and operation method thereof
Jooyong Park, Suwon-si (KR); Wontaeck Jung, Suwon-si (KR); Nayeon Kim, Suwon-si (KR); Jiwon Seo, Suwon-si (KR); and Seungyong Hyun, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 8, 2022, as Appl. No. 17/982,550.
Claims priority of application No. 10-2021-0155153 (KR), filed on Nov. 11, 2021; and application No. 10-2022-0063678 (KR), filed on May 24, 2022.
Prior Publication US 2023/0148408 A1, May 11, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/3468 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of programming memory cells of a memory device to a plurality of program states, the method comprising, for a target program state of the plurality of program states:
(a) selecting one or more of the memory cells to be programmed to the target program state, the selected memory cells being connected to a selected word line;
(b) applying one or more program pulses to the selected memory cells;
(c) performing a first verification operation of verifying the selected memory cells as programmed to at least the target program state, the verified selected memory cells being identified as programmed-passed memory cells, the first verification operation comprising providing a first verify voltage to the selected memory cells;
(d) after the first verification operation is passed for all of the selected memory cells, performing a second verification operation of detecting fail cells among the programmed-passed memory cells, the second verification operation comprising providing an over-bit verify voltage to the programmed-passed memory cells; and
(e) comparing a number of detected fail cells to a reference value to determine whether a program operation should be terminated,
wherein the over-bit verify voltage provided to the programmed-passed memory cells in the second verification operation comprises a verify voltage corresponding to a subsequent program state to the target program state,
wherein a first voltage is applied to an unselected word line during the first verification operation,
wherein a second voltage is applied to the unselected word line during the second verification operation, and
wherein the first voltage and the second voltage are different from each other.