US 12,340,848 B2
Memory device and operating method thereof
Cheol Joong Park, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Aug. 9, 2022, as Appl. No. 17/883,719.
Claims priority of application No. 10-2022-0031969 (KR), filed on Mar. 15, 2022.
Prior Publication US 2023/0298670 A1, Sep. 21, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/08 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory device comprising:
a target memory block on which an erase operation is to be performed; and
a peripheral circuit,
wherein
the peripheral circuit, during the erase operation, floats local word lines which are coupled to the target memory block while the erase voltage rises toward a target level,
the peripheral circuit, during the erase operation and after an erase voltage reached the target level, applies a first voltage to the local word lines, and
the peripheral circuit, during the erase operation and after application of the first voltage to the local word lines, applies one or more group voltages to the local word lines.