US 12,340,845 B2
Split block array for 3D NAND memory
Chang Wan Ha, San Ramon, CA (US); Deepak Thimmegowda, Fremont, CA (US); Hoon Koh, San Jose, CA (US); Richard M. Gularte, Santa Clara, CA (US); Liu Liu, Dalian (CN); David Meyaard, Boise, ID (US); and Ahsanur Rahman, Santa Clara, CA (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by INTEL NDTM US LLC, Santa Clara, CA (US)
Filed on Jun. 9, 2021, as Appl. No. 17/343,584.
Prior Publication US 2022/0399057 A1, Dec. 15, 2022
Int. Cl. G11C 16/04 (2006.01)
CPC G11C 16/0483 (2013.01) 12 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a full block memory array of each of a lower tile and an upper tile of 3D NAND string memory cells, wherein:
along a first lateral length of a staircase structure passing through the lower tile and the upper tile, the full block memory array comprises a first plurality of bit line exits where there are no memory cells, the first plurality of bit line exits extending a second lateral length, orthogonal to the first lateral length, from a first side of the full block memory array, and terminating at the staircase structure; and
along a second lateral length of the staircase structure, the full block memory array comprises a second plurality of bit line exits where there are no memory cells, the second plurality of bit line exits extending a third lateral length, orthogonal to the first lateral length, from a second, opposite, side of the full block memory array, and terminating at the staircase structure;
a split block memory array of each of the lower tile and the upper tile of the 3D NAND string memory cells, wherein:
along the first lateral length of the staircase structure, the split block memory array comprises a first plurality of split blocks of memory cells colinear with corresponding ones of the first plurality of bit line exits, the first plurality of split blocks extending the third lateral length from the second, opposite, side of the full block memory array, and terminating at the staircase structure; and
along the second lateral length of the staircase structure, the split block memory array comprises a second plurality of split blocks of memory cells colinear with corresponding ones of the second plurality of bit line exits, the second plurality of split blocks extending the second lateral length from the first side of the full block memory array, and terminating at the staircase structure;
a first portion of a string driver circuit coupled to the full block memory array and to the split block memory array of the lower tile; and
a second portion of the string driver circuit coupled to the full block memory array and to the split block memory array of the upper tile.