| CPC G11C 11/54 (2013.01) | 20 Claims |
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1. A system comprising a plurality of first memory cells and a transistor, wherein the plurality of first memory cells comprises:
a first memory cell configured to generate a first signal at a first node based on a first bit, the first memory cell comprising:
a first switch;
a first memory element; and
a second memory element coupled to the first memory element at the first node, and configured to store the first bit with the first memory element; and
a second memory cell configured to generate a second signal at a second node based on a second bit, the second memory cell comprising:
a third memory element; and
a fourth memory element coupled to the third memory element at the second node, and configured to store the second bit with the third memory element,
wherein the first memory cell and the second memory cell are configured to cooperate with each other to generate a first weight signal corresponding to at least the first bit and the second bit, based on at least the first signal and the second signal,
the first memory element and the second memory element are coupled to two terminals of the first switch, respectively, and
the transistor is configured to provide a bit line signal to a gate terminal of the first switch according to a word line signal.
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