US 12,340,838 B2
Drive circuit with improved timing margin for memory device
Masaru Haraguchi, Hsinchu (TW); Yoshisato Yokoyama, Hsinchu (TW); and Yorinobu Fujino, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 30, 2023, as Appl. No. 18/103,364.
Claims priority of provisional application 63/388,779, filed on Jul. 13, 2022.
Prior Publication US 2024/0021241 A1, Jan. 18, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell;
a drive circuit coupled to a first line and a second line, the drive circuit configured to apply, according to a first control signal having a first state, a data signal to either one of the first line or the second line to write data at the memory cell;
a pre-charge circuit coupled to the first line and the second line, the pre-charge circuit configured to set, according to a second control signal having a second state and the first control signal having a third state, voltages at the first line and the second line to a predetermined voltage level; and
an equalizer coupled between the first line and the second line, the equalizer configured to electrically couple the first line to the second line, based on a logic combination of the second control signal and the first control signal, where the second control signal has the second state and the first control signal has the third state.