| CPC G09G 3/3258 (2013.01) [H10K 59/1213 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0214 (2013.01); G09G 2320/045 (2013.01); G09G 2330/06 (2013.01)] | 20 Claims |

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1. A pixel driving circuit, comprising:
a driving circuit, connecting a first node, a second node, and a third node, and configured to provide, based on a voltage of the first node, a driving current to the third node by using the second node;
a compensation circuit, connecting the third node, a fourth node, and a first gate driving signal end, and configured to conduct the third node and the fourth node in response to a signal of the first gate driving signal end;
a first reset circuit, connecting a first initial signal end, a fifth node, and a first reset signal end, and configured to transmit a signal of the first initial signal end to the fifth node in response to a signal of the first reset signal end;
a first isolation circuit, connecting the first node and the fourth node, and configured to conduct the first node and the fourth node in response to a control signal, wherein the control signal of the first isolation circuit is different from the signal of the first gate driving signal end; and
a second isolation circuit, connecting the first node and the fifth node, and configured to conduct the first node and the fifth node in response to another control signal, wherein the another control signal of the second isolation circuit is different from the signal of the first reset signal end.
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