US 12,340,732 B2
Pixel driving circuit with pulse amplitude and width modulation, driving method thereof, and display panel
Yanyan Wu, Guangdong (CN); and Lijun Zhang, Guangdong (CN)
Assigned to Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen (CN)
Filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Guangdong (CN)
Filed on Oct. 22, 2023, as Appl. No. 18/491,774.
Claims priority of application No. 202311044976.4 (CN), filed on Aug. 18, 2023.
Prior Publication US 2025/0061839 A1, Feb. 20, 2025
Int. Cl. G09G 3/32 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 2300/0852 (2013.01); G09G 2310/0262 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0219 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A pixel driving circuit, comprising:
a light emitting device electrically connected between a first node and a first voltage terminal;
a driving transistor electrically connected to the first node, a second node, and a second voltage terminal, wherein the driving transistor is configured to generate a driving current to drive the light emitting device to emit light;
a pulse amplitude modulation subcircuit electrically connected to the driving transistor and configured to output a pulse amplitude modulation voltage to the driving transistor to control an amplitude of the driving current; and
a pulse width modulation subcircuit electrically connected to the second node, the second voltage terminal, and the pulse amplitude modulation subcircuit and configured to control a duration of the driving transistor outputting the driving current according to a sweep voltage,
wherein the driving transistor has a control terminal electrically connected to the second node, an input terminal electrically connected to the light emitting device, and an output terminal electrically connected to the second voltage terminal; and
wherein the pulse amplitude modulation subcircuit comprises:
a first compensation transistor having a control terminal electrically connected to a compensation control line, an input terminal electrically connected to the first node, and an output terminal electrically connected to the second node;
a first reset transistor having a control terminal electrically connected to a first reset control line, an input terminal electrically connected to the second voltage terminal, and an output terminal electrically connected to a third node;
a first data transistor having a control terminal electrically connected to a pulse amplitude control line, an input terminal electrically connected to a data line, and an output terminal electrically connected to the third node;
a first capacitor connected in series between the second node and the second voltage terminal;
a second capacitor connected in series between the second node and the third node; and
a second reset transistor having a control terminal electrically connected to a second reset control line, an input terminal electrically connected to the data line, and an output terminal electrically connected to the second node.