US 12,340,504 B2
Semiconductor inspecting method and semiconductor inspecting device
Akira Shimase, Hamamatsu (JP); Xiangguang Mao, Hamamatsu (JP); and Akihito Uchikado, Hamamatsu (JP)
Assigned to HAMAMATSU PHOTONICS K.K., Hamamatsu (JP)
Appl. No. 17/925,625
Filed by HAMAMATSU PHOTONICS K.K., Hamamatsu (JP)
PCT Filed Mar. 31, 2021, PCT No. PCT/JP2021/013840
§ 371(c)(1), (2) Date Nov. 16, 2022,
PCT Pub. No. WO2021/250984, PCT Pub. Date Dec. 16, 2021.
Claims priority of application No. 2020-099463 (JP), filed on Jun. 8, 2020.
Prior Publication US 2023/0206422 A1, Jun. 29, 2023
Int. Cl. G06T 7/00 (2017.01); G01R 31/308 (2006.01); G06V 10/764 (2022.01)
CPC G06T 7/001 (2013.01) [G01R 31/308 (2013.01); G06V 10/764 (2022.01); G06T 2207/10024 (2013.01); G06T 2207/20081 (2013.01); G06T 2207/20212 (2013.01); G06T 2207/30148 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor inspecting method comprising:
scanning a semiconductor device with light to acquire characteristic information indicative of characteristics of an electrical signal of the semiconductor device in response to irradiation with the light for each of irradiation positions of the light and to generate a first pattern image of the semiconductor device based on the characteristic information for each of the irradiation positions;
generating a second pattern image of the semiconductor device based on a layout image showing a layout of the semiconductor device and current path information indicative of a current path in the semiconductor device; and
acquiring matching information indicative of a relative relationship between the first pattern image and the layout image based on a result of positional alignment between the first pattern image and the second pattern image.