| CPC G06Q 40/04 (2013.01) [G06F 17/18 (2013.01); G06N 20/00 (2019.01); G06Q 30/0201 (2013.01)] | 26 Claims |

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1. A field programmable gate array (FPGA) or graphics processor unit (GPU) for accelerated processing of streaming financial market data that pertains to a plurality of financial instruments to derive trading signals at low latency, the FPGA or GPU comprising:
a plurality of feature compute stage circuits arranged in parallel to define a plurality of parallel paths within the FPGA or GPU, wherein the parallel feature compute stage circuits comprise parallelized hardware logic and state memory that are configured to compute a plurality of features of the streaming financial market data in parallel; and
a combine stage circuit connected to the feature compute stage circuits, wherein the combine stage circuit comprises parallelized hardware logic configured to compute a hidden liquidity size estimation based on a weighted combination of the computed features, wherein the hidden liquidity size estimation represents an estimated size of a hidden order for a financial instrument, wherein each computed feature has a corresponding weight for the weighted combination;
wherein the computed features comprise features that are correlated to and predictive of the estimated size for the hidden order; and
wherein a selection of which features to use for the correlated and predictive features and what values to use for the corresponding weights are derived from a supervised machine learning model.
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