US 12,340,304 B2
Partial sum management and reconfigurable systolic flow architectures for in-memory computation
Mustafa Badaroglu, Flemish Brabant (BE); and Zhongze Wang, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 10, 2021, as Appl. No. 17/398,791.
Prior Publication US 2023/0047364 A1, Feb. 16, 2023
Int. Cl. G06N 3/063 (2023.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06N 3/08 (2023.01); G06F 7/544 (2006.01)
CPC G06N 3/08 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06N 3/063 (2013.01); G06F 7/5443 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A processing element (PE) circuit comprising:
a first accumulator circuit;
a flip-flop array having an input coupled to an output of the first accumulator circuit;
a write register;
a first multiplexer having a first input coupled to an output of the write register, having a second input coupled to an output of the flip-flop array, and having an output coupled to a first input of the first accumulator circuit;
an adder circuit; and
an accumulator-and-shifter circuit having an input coupled to an output of the adder circuit and having an output coupled to a second input of the first accumulator circuit.