US 12,340,273 B2
Quantum processor unit architecture for quantum computing via an arbitrarily programmable interaction connectivity graph
Irfan Siddiqi, Berkeley, CA (US); Jie Luo, Berkeley, CA (US); and Brian Marinelli, Berkeley, CA (US)
Assigned to THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Oakland, CA (US)
Filed by THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Oakland, CA (US)
Filed on Nov. 4, 2021, as Appl. No. 17/519,320.
Claims priority of provisional application 63/109,516, filed on Nov. 4, 2020.
Prior Publication US 2022/0138611 A1, May 5, 2022
Int. Cl. G06N 10/40 (2022.01); G01R 33/035 (2006.01)
CPC G06N 10/40 (2022.01) [G01R 33/0358 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A superconducting quantum processor unit apparatus for quantum computing, the apparatus comprising:
(a) a qubit chip, comprising:
(i) a planar substrate with a plurality of qubit chip surface bonding elements;
(ii) a plurality of qubits; and
(iii) a probe line inductively coupled to the qubits;
(b) a wiring chip, comprising:
(i) a planar substrate with a plurality of wiring chip surface bonding elements;
(ii) a bus coupling resonator with a plurality of voltage nodes and anti-nodes;
(iii) at least one Superconducting-Quantum-Interference-Device (SQUID) joined to the bus coupling resonator; and
(iv) a resonator pump connected to said bus coupling resonator through pump capacitors at said voltage anti-nodes;
(c) wherein said qubit chip is mounted to said wiring chip with the surface bonding elements of each chip to produce a superconducting quantum processor unit.