| CPC G06F 9/522 (2013.01) [G06F 9/30087 (2013.01); G06F 9/3851 (2013.01); G06F 9/3888 (2023.08)] | 20 Claims |
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1. A computer-implemented method for synchronizing threads executing in a processor, the method comprising:
determining that a first thread has executed a first memory barrier instruction, wherein the first thread is included in a first set of threads associated with a first domain representing a first set of resources included in the processor that synchronize with one another;
determining a set of memory apertures associated with the first domain that have been accessed by at least one thread included in the first set of threads;
generating a memory barrier command that:
specifies references to the set of memory apertures associated with the first domain to flush in response to the memory barrier command, and
excludes references to other memory apertures that are excluded from being flushed in response to the memory barrier command, wherein the other memory apertures are accessed by threads associated with a second domain representing a second set of resources included in the processor that synchronize with one another, and wherein the second set of resources is different from the first set of resources; and
transmitting the memory barrier command to the set of memory apertures.
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