US 12,340,227 B2
Sparse SIMD cross-lane processing unit
Rahul Nagarajan, San Jose, CA (US); Suvinay Subramanian, Sunnyvale, CA (US); and Arpith Chacko Jacob, Los Altos, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Mar. 6, 2024, as Appl. No. 18/597,005.
Application 18/597,005 is a continuation of application No. 17/972,663, filed on Oct. 25, 2022, granted, now 11,966,745.
Claims priority of provisional application 63/279,262, filed on Nov. 15, 2021.
Prior Publication US 2024/0211269 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3887 (2013.01) [G06F 9/30036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A hardware circuit, comprising:
a plurality of stages, each stage comprising a crossbar and a plurality of cells; and
a plurality of data processing lanes streaming data from an upstream input to a downstream destination through the crossbar and a plurality of cells of respective stages;
wherein the hardware circuit is configured to:
receive input data and instructions for performing a first operation from the upstream input;
for each stage, send respective instructions to the crossbar and plurality of cells, the crossbar configured to permute outputs along the plurality of data processing lanes, the plurality of cells configured to perform respective processing operations based on the instructions; and
perform the first operation by processing the received input data along the plurality of data processing lanes.