US 12,340,226 B2
Vector instruction cracking after scalar dispatch
Kathlene Rose Magnus, San Antonio, TX (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Sep. 18, 2023, as Appl. No. 18/469,008.
Claims priority of provisional application 63/415,473, filed on Oct. 12, 2022.
Prior Publication US 2024/0126556 A1, Apr. 18, 2024
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3867 (2013.01) [G06F 9/30036 (2013.01); G06F 9/3856 (2023.08)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a primary pipeline configured to:
determine a type of instruction;
responsive to a determination that the instruction is a vector instruction, create a reorder buffer entry in a reorder buffer for the vector instruction prior to out-of-order processing in the primary pipeline; and
send the vector instruction to a vector pipeline; and
the vector pipeline configured to process the vector instruction.