| CPC G06F 9/30181 (2013.01) [G06F 9/30032 (2013.01); G06F 9/30043 (2013.01)] | 20 Claims |
|
1. A processor, comprising:
operand management circuitry including a fusion buffer, wherein the operand management circuitry is configured to:
receive instruction operations;
detect, from among the received instruction operations, a first storage instruction operation that is executable to store, into one or more destination registers, one or more first operand values usable by one or more consumer instruction operations;
store the first storage instruction operation in the fusion buffer instead of allowing the first storage instruction operation to proceed along an execution pipeline of the processor;
in response to detecting a drop condition associated with the first storage instruction operation, remove the first storage instruction operation from the fusion buffer without forwarding the first storage instruction operation for execution, so that the one or more first operand values are not written to the one or more destination registers; and
in response to detecting a buffer vacate condition and not detecting the drop condition, remove the first storage instruction operation from the fusion buffer and forward the first storage instruction operation for execution; and
execution circuitry coupled to the operand management circuitry and configured to execute instruction operations including the first storage instruction operation.
|