US 12,340,164 B2
Methods and systems for reticle enhancement technology of a design pattern to be manufactured on a substrate
Akira Fujimura, Saratoga, CA (US); P. Jeffrey Ungar, Belmont, CA (US); and Nagesh Shirali, San Jose, CA (US)
Assigned to D2S, Inc., San Jose, CA (US)
Filed by D2S, Inc., San Jose, CA (US)
Filed on May 7, 2024, as Appl. No. 18/657,435.
Application 18/657,435 is a continuation of application No. 18/318,602, filed on May 16, 2023, granted, now 12,019,973.
Application 18/318,602 is a continuation of application No. 17/444,140, filed on Jul. 30, 2021, granted, now 11,783,110, issued on Oct. 10, 2023.
Prior Publication US 2024/0289532 A1, Aug. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G03F 7/00 (2006.01); G03F 1/36 (2012.01); G03F 1/70 (2012.01); G03F 1/74 (2012.01); G03F 1/78 (2012.01); G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/398 (2020.01) [G03F 1/36 (2013.01); G03F 1/70 (2013.01); G03F 1/74 (2013.01); G03F 1/78 (2013.01); G03F 7/70441 (2013.01); G03F 7/705 (2013.01); G06F 2119/18 (2020.01)] 17 Claims
OG exemplary drawing
 
16. A method for manufacturing a semiconductor device on a substrate, the method comprising:
providing an optimized mask pattern simulated from a modified set of VSB shots;
optimizing the modified set of VSB shots for wafer quality by comparing a first substrate pattern and a second substrate pattern, wherein the second substrate pattern is calculated from the optimized mask pattern simulated from the modified set of VSB shots; and
exposing a reticle with the modified set of VSB shots;
wherein the first substrate pattern is calculated from an initial mask pattern.