US 12,340,126 B2
Workload-based scan optimization
Kishore Kumar Muchherla, San Jose, CA (US); Eric N. Lee, San Jose, CA (US); Jeffrey S. McNeil, Nampa, ID (US); Jonathan S. Parry, Boise, ID (US); and Lakshmi Kalpana Vakati, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 1, 2024, as Appl. No. 18/623,881.
Application 18/623,881 is a continuation of application No. 17/691,014, filed on Mar. 9, 2022, granted, now 11,977,778.
Prior Publication US 2024/0248646 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a plurality of memory units; and
a processing device, operatively coupled to the memory device, to perform processing operations comprising:
identifying one or more operating characteristic values of the memory device;
determining whether the one or more operating characteristic values satisfy one or more threshold criteria; and
responsive to determining that the one or more operating characteristic values satisfy the one or more threshold criteria:
performing a plurality of write operations on the plurality of memory units, wherein each of the plurality of write operations writes corresponding data to a respective one of the plurality of memory units, and
performing a multiple-read scan operation subsequent to the plurality of write operations, wherein the multiple-read scan operation reads data from each of the plurality of memory units.