US 12,340,123 B2
Memory systems, modules, and methods for improved capacity
Frederick A. Ware, Los Altos Hills, CA (US); and Scott C. Best, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Oct. 29, 2023, as Appl. No. 18/496,887.
Application 18/496,887 is a continuation of application No. 17/235,629, filed on Apr. 20, 2021, granted, now 11,853,600.
Application 17/235,629 is a continuation of application No. 16/599,891, filed on Oct. 11, 2019, granted, now 11,010,098, issued on May 18, 2021.
Application 16/599,891 is a continuation of application No. 15/522,164, granted, now 10,459,660, issued on Oct. 29, 2019, previously published as PCT/US2015/058946, filed on Nov. 4, 2015.
Claims priority of provisional application 62/082,286, filed on Nov. 20, 2014.
Prior Publication US 2024/0111457 A1, Apr. 4, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 5/04 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0629 (2013.01); G06F 3/0673 (2013.01); G06F 13/1673 (2013.01); G11C 5/04 (2013.01); Y02D 10/00 (2018.01)] 10 Claims
OG exemplary drawing
 
1. A memory module comprising:
a memory device;
a command input port to receive module commands;
command logic coupled between the command input port and the memory device, the command logic to issue memory-device commands to the memory device responsive to the module commands and including a selectable command-delay element to selectively impose or omit a propagation delay on the memory-device commands relative to the module commands; and
a command-relay circuit coupled to the command input port, the command-relay circuit to relay the module commands away from the memory module;
wherein the command-relay circuit, when enabled, imposes the same propagation delay imposed by the selectable command-delay element on the memory-device commands relative to the module commands.