US 12,340,101 B2
Scaling out architecture for dram-based processing unit (DPU)
Dimin Niu, Sunnyvale, CA (US); Shuangchen Li, Goleta, CA (US); Bob Brennan, San Jose, CA (US); Krishna T. Malladi, San Jose, CA (US); and Hongzhong Zheng, Los Gatos, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 2, 2024, as Appl. No. 18/593,885.
Application 18/593,885 is a continuation of application No. 16/942,641, filed on Jul. 29, 2020, granted, now 11,934,669.
Application 16/942,641 is a continuation of application No. 15/595,887, filed on May 15, 2017, granted, now 10,732,866, issued on Aug. 4, 2020.
Claims priority of provisional application 62/485,370, filed on Apr. 13, 2017.
Claims priority of provisional application 62/414,426, filed on Oct. 28, 2016.
Claims priority of provisional application 62/413,977, filed on Oct. 27, 2016.
Claims priority of provisional application 62/413,973, filed on Oct. 27, 2016.
Prior Publication US 2024/0211149 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 15/78 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 3/0631 (2013.01) [G06F 3/0604 (2013.01); G06F 3/067 (2013.01); G06F 15/7821 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
programmable memory configured to operate as a computation unit, and reconfigurable to perform storage operations based on a configuration for additional memory,
wherein the programmable memory comprises an interface to change the configuration for the additional memory.