US 12,340,099 B2
Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertion
Praveen Kumar Verma, Greater Noida (IN); and Harsh Rawat, Faridabad (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on May 11, 2023, as Appl. No. 18/196,152.
Application 18/196,152 is a continuation in part of application No. 17/861,384, filed on Jul. 11, 2022, granted, now 12,040,013.
Claims priority of provisional application 63/231,851, filed on Aug. 11, 2021.
Prior Publication US 2023/0280915 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A circuit that is clocked by a clock signal, comprising:
a memory array including memory cells forming a data word location accessed in response to a modulated word line signal;
a plurality of bit lines associated with said memory cells;
a data sensing circuit configured when the modulated word line signal has a first voltage level to sense data on said plurality of bit lines, said sensed data corresponding to a current data word stored at the data word location;
a data latching circuit configured to latch the sensed data for said current data word from the data sensing circuit;
a data modification circuit configured when the modulated word line signal has a second voltage level lower than the first voltage level to perform an internal memory mathematical modify operation on the current data word to generate a modified data word; and
a data writing circuit configured when the modulated word line signal has the first voltage level to apply data for the modified data word to the plurality of bit lines for writing back to the memory cells of the memory array at said data word location;
wherein the sensing of the data on said plurality of bit lines, the latching of the sensed data, the performing of the internal memory mathematical modify operation and the writing back of the modified data word all occur within a single cycle of the clock signal.