CPC G06F 21/575 (2013.01) | 14 Claims |
1. A secure boot device, comprising:
a first counter, configured to receive a first clock,
wherein when a processor performs a verification of a firmware for a first time, the first counter counts a first verification time taken by the processor to perform the verification of the firmware for the first time based on the first clock to generate a first first-time verification count value, and
wherein when the processor performs the verification of the firmware for a non-first time, the first counter counts a second verification time taken by the processor to perform the verification of the firmware at least once for the non-first time based on the first clock to generate a first count value;
a first storage device, electrically connected to the first counter, and configured to store the first first-time verification count value; and
a first comparator, electrically connected to the first counter and the first storage device,
wherein when the processor performs the verification of the firmware for the non-first time, the first comparator compares the first count value with the first first-time verification count value and generates a first comparison result, and
wherein the first comparison result is configured to indicate whether the processor executes the firmware.
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