| CPC G06F 21/33 (2013.01) [G06F 21/53 (2013.01); G06F 2221/031 (2013.01)] | 18 Claims |

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1. A first apparatus, comprising:
at least one processor; and
at least one memory including computer program code;
wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the first apparatus to:
transmit, to a second apparatus, a request for execution of a task, the task comprising a plurality of functions to be executed;
generate a first validation key from identification information of the plurality of functions based on an expected execution plan in at least one trusted execution environment of the second apparatus;
receive, from the second apparatus, an execution result for the task and a second validation key; and
determine correctness of the execution result by comparing the first validation key with the second validation key,
wherein the expected execution plan at least indicates an execution order of the plurality of functions, and wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the first apparatus to generate the first validation key by:
generating intermediate keys for the plurality of functions in the execution order, an intermediate key for a function being determined at least based on an intermediate key for a predecessor function of the function in the execution order; and
determining the first validation key based on the generated intermediate key for a last function of the plurality of functions.
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