US 12,339,923 B2
Permuting in a matrix-vector processor
Dong Hyuk Woo, San Jose, CA (US); Gregory Michael Thorson, Waunakee, WI (US); Andrew Everett Phelps, Middleton, WI (US); Olivier Temam, Antony (FR); Jonathan Ross, Mountain View, CA (US); and Christopher Aaron Clark, Madison, WI (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Sep. 1, 2023, as Appl. No. 18/241,805.
Application 18/241,805 is a continuation of application No. 17/208,214, filed on Mar. 22, 2021, granted, now 11,748,443.
Application 17/208,214 is a continuation of application No. 16/840,972, filed on Apr. 6, 2020, granted, now 10,956,537, issued on Mar. 23, 2021.
Application 16/840,972 is a continuation of application No. 16/528,826, filed on Aug. 1, 2019, granted, now 10,614,151, issued on Apr. 7, 2020.
Application 16/528,826 is a continuation of application No. 16/283,913, filed on Feb. 25, 2019, granted, now 10,592,583, issued on Mar. 17, 2020.
Application 16/283,913 is a continuation of application No. 15/966,275, filed on Apr. 30, 2018, granted, now 10,216,705, issued on Feb. 26, 2019.
Application 15/966,275 is a continuation of application No. 15/496,418, filed on Apr. 25, 2017, granted, now 9,959,247, issued on May 1, 2018.
Claims priority of provisional application 62/460,394, filed on Feb. 17, 2017.
Prior Publication US 2024/0211534 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 17/16 (2006.01); G06F 7/76 (2006.01); G06F 9/30 (2018.01); G06N 3/063 (2023.01); G06N 3/084 (2023.01)
CPC G06F 17/16 (2013.01) [G06F 7/76 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06N 3/063 (2013.01); G06N 3/084 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A special-purpose hardware integrated circuit, the circuit comprising:
a memory configured to store an input matrix and an output matrix;
a permute unit coupled to the memory, wherein the permute unit comprises:
an input register that stores input vectors corresponding to the input matrix;
a control register configured to store a control vector of control signals;
a permute execution circuit coupled to the input register and the control register, the permute execution circuit being configured to:
i) compute a matrix permutation of the input matrix by permuting the input vectors based on the control signals of the control vector; and
ii) generate the output matrix as a permutation of the input matrix.