| CPC G06F 12/1425 (2013.01) [G06F 12/1483 (2013.01); G06F 2212/1052 (2013.01)] | 14 Claims |

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1. A method for managing a cache memory provided to equip an electronic device comprising a processor and a main memory, wherein the managing cache memory comprises the following steps:
generating a random value for each process of accessing the cache memory,
transforming addresses of the cache memory with said random value into corresponding addresses, referred to as randomized addresses being configured to index the cache memory,
associating each random value corresponding to an access process, with an identifier of said access process, forming pairs of identifications that are configured to dynamically partition the cache memory while registering the access to said cache memory,
storing each identification pair composed of a random value and of a corresponding identifier in a history table, and
managing each process of accessing the cache memory according to said identification pairs stored in said history table.
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