US 12,339,780 B2
Multi-mode indexed cache in a processor
Pranjal Kumar Dutta, Sunnyvale, CA (US)
Assigned to Nokia Solutions and Networks Oy, Espoo (FI)
Filed by Nokia Solutions and Networks Oy, Espoo (FI)
Filed on Jan. 16, 2023, as Appl. No. 18/097,421.
Prior Publication US 2024/0241832 A1, Jul. 18, 2024
Int. Cl. G06F 12/0864 (2016.01); G06F 12/0895 (2016.01)
CPC G06F 12/0864 (2013.01) [G06F 12/0895 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a cache configured as a set associative cache having a plurality of sets, wherein the cache is configured to support multiple indexing modes for indexing memory blocks such that, for a memory operation for a given memory block, the multiple indexing modes are configured to cause selection of different ones of the plurality of sets of the cache for the memory operation for the given memory block, wherein the multiple indexing modes are configured to use disjoint subsets of bits of a memory block address of the given memory block to cause selection of the different ones of the plurality of sets of the cache for the memory operation for the given memory block.