US 12,339,775 B2
Hardware accelerator for hypergraph processing and operating method thereof
Long Zheng, Wuhan (CN); Qinggang Wang, Wuhan (CN); Xiaofei Liao, Wuhan (CN); Ao Hu, Wuhan (CN); and Hai Jin, Wuhan (CN)
Assigned to Huazhong University of Science and Technology, Wuhan (CN); and Zhejiang Lab, Wuhan (CN)
Filed by Huazhong University Of Science And Technology, Wuhan (CN); and Zhejiang Lab, Hangzhou (CN)
Filed on Dec. 22, 2022, as Appl. No. 18/145,565.
Claims priority of application No. 202210990115.4 (CN), filed on Aug. 17, 2022.
Prior Publication US 2024/0061779 A1, Feb. 22, 2024
Int. Cl. G06F 12/0806 (2016.01); G06F 12/10 (2016.01)
CPC G06F 12/0806 (2013.01) [G06F 12/10 (2013.01); G06F 2212/1016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A hardware accelerator for hypergraph processing, at least comprising:
a data loader, configured to, in the presence of a data-centric load-trigger-reduce execution model, read hypergraph partitioning data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions;
an address translator, configured to deploy the hypergraph partitioning data into at least one of a private register of a processor and a buffer memory according to a priority level of loaded data, and to record corresponding offset information into a Hash table;
a task trigger, configured to generate computing tasks according to the loaded data, and to schedule the computing tasks into the processor;
the processor, comprising at least one processing unit, which receives and executes the computing tasks;
a reducer, configured to schedule intermediate results into a first-priority-data reducer unit in response to determining the priority level of the loaded data is a first-priority level or a second-priority-data reducer unit in response to determining the priority level of the loaded data is a second-priority level so as to execute a reducing operation for the intermediate results.