| CPC G06F 12/0246 (2013.01) | 20 Claims |
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1. A memory device, comprising:
a memory cell array, and
a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to:
receive a first instruction indicating to write dummy data at a specified location in the memory cell array;
generate the dummy data to be written in response to the first instruction;
write the dummy data to be written at the specified location;
receive a second instruction indicating to perform a read operation on data in the memory cell array; and
return the data to be read in response to the second instruction,
wherein, when the data to be read comprises the dummy data, a second flag is set on a reserved field of a frame header of a returned data frame, and the second flag indicates that read data comprises the dummy data.
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