US 12,339,762 B2
Method for monitoring an execution of a program code portion and corresponding system-on-chip
Michel Jaouen, Yvre L'eveque (FR); and Loic Pallardy, Rouillon (FR)
Assigned to STMicroelectronics (Grand Ouest) SAS, Le Mans (FR)
Filed by STMicroelectronics (Grand Ouest) SAS, Le Mans (FR)
Filed on Apr. 24, 2023, as Appl. No. 18/306,032.
Claims priority of application No. 2203873 (FR), filed on Apr. 26, 2022.
Prior Publication US 2023/0342279 A1, Oct. 26, 2023
Int. Cl. G06F 11/34 (2006.01); G06F 11/3604 (2025.01)
CPC G06F 11/3466 (2013.01) [G06F 11/3612 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address, the execution implemented by processing circuitry using a program counter pointing to an address of an instruction executed by the processing circuitry, the method comprising:
starting a timer in response to the program counter pointing to the start address of the selected program code portion;
comparing current values of the program counter with a set of target addresses specific to the selected program code portion, the set of target addresses including the end address of the selected program code portion;
stopping the timer in response to the program counter pointing to the end address of the selected program code portion;
comparing a duration of starting the timer and stopping the timer to a threshold specific to the selected program code portion, wherein the threshold is automatically adjusted based on a frequency of a clock signal clocking the execution of the processing circuitry, a cache instruction admission event, a cache data admission event, a cache data eviction event, a wait state of the processing circuitry, or a combination thereof; and
generating an error signal in response to the duration being greater or less than the threshold.