US 12,339,745 B1
Solid-state drive with multimode compression and error correction
Tong Zhang, Albany, NY (US); Mark Vernon, San Jose, CA (US); Jiangpeng Li, San Jose, CA (US); Yang Liu, Milpitas, CA (US); and Fei Sun, Irvine, CA (US)
Assigned to SCALEFLUX, INC., San Jose, CA (US)
Filed by ScaleFlux, Inc., San Jose, CA (US)
Filed on Apr. 22, 2024, as Appl. No. 18/641,942.
Int. Cl. G06F 11/10 (2006.01); G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 12/02 (2006.01); H03M 13/00 (2006.01); H04L 1/00 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/00 (2013.01); G06F 11/0703 (2013.01); G06F 11/0727 (2013.01); G06F 12/0246 (2013.01); H03M 13/618 (2013.01); H03M 13/6362 (2013.01); H04L 1/0008 (2013.01); H04L 1/0068 (2013.01); H04L 1/0069 (2013.01); H04L 2209/20 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A multimode solid-state drive (SSD), comprising:
a plurality of flash memory chips (flash memory) addressable via physical block addresses (PBAs); and
a controller chip that utilizes a mapping table to map logical block addresses (LBAs) to PBAs, wherein the controller chip includes a general-purpose mode and a zero-padding mode for providing compression and error correction coding (ECC) and implements a process that includes:
in response to a determination that a data item is to be written into flash memory using the zero-padding mode:
padding the data item with an all-zero tail to form an LBA data block of a predefined size;
performing ECC coding on the LBA block to generate an ECC codeword;
removing the all-zero tail from the ECC codeword to generate a shortened ECC codeword; and
storing the shortened ECC codeword in flash memory.