US 12,339,744 B2
Dynamic parity scheme
Gennaro Schettino, Casamicciola Terme (IT); and Luca Porzio, Casalnuovo (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 3, 2024, as Appl. No. 18/626,135.
Application 18/626,135 is a continuation of application No. 17/888,299, filed on Aug. 15, 2022, granted, now 11,977,443.
Prior Publication US 2024/0345921 A1, Oct. 17, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 13/28 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/108 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A method for memory operations, comprising:
performing a first access operation according to a parity scheme at a plurality of blocks of memory cells storing data and parity information associated with the data;
adjusting, after performing the first access operation, the parity scheme for one or more blocks of memory cells of the plurality of blocks of memory cells; and
performing a second access operation according to the adjusted parity scheme at the one or more blocks of memory cells.