US 12,339,743 B2
ECC decoder and memory controller including the same
Soonyoung Kang, Suwon-si (KR); Yongsung Kil, Suwon-si (KR); Jaehong Kim, Suwon-si (KR); and Hongrak Son, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 26, 2023, as Appl. No. 18/495,156.
Claims priority of application No. 10-2022-0140503 (KR), filed on Oct. 27, 2022.
Prior Publication US 2024/0143442 A1, May 2, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0772 (2013.01); G06F 11/1048 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a processor having a decoding-mode determination circuit therein, which is configured to: (i) receive information on a lifespan or retention of a memory device, and (ii) based on the received information, determine one of a first operation mode and a second operation mode as an operation mode, said processor configured to transmit to the memory device, a coarse soft decision (SD) read command for obtaining hard decision (HD) data and a first piece of SD data during a time period of a single read, or a fine SD read command for obtaining a second piece of SD data from a plurality of reads; and
an error correction code (ECC) decoder including: (i) a coarse SD setting circuit configured to store a parameter value of a decoding operation, which is based on the first piece of SD data obtained by the coarse SD read command, (ii) a fine SD setting circuit configured to store a parameter value of a decoding operation, which is based on the second piece of SD data obtained by the fine SD read command, and (iii) a decoding circuit configured to perform iterative decoding based on the first piece of SD data or the second piece of SD data;
wherein the first operation mode corresponds to a mode for sequentially transmitting the coarse SD read command and the fine SD read command to the memory device;
wherein the second operation mode corresponds to a mode for transmitting the fine SD read command to the memory device, and
wherein the decoding-mode determination circuit is further based on a syndrome value indicating a number of non-zero bits included in results of an operation on previous hard decision decoding results and parity check matrix.