US 12,339,742 B2
Soft read operations with progressive data output
Ali Khakifirooz, Brookline, MA (US); George Kalwitz, Mead, CO (US); Anand Ramalingam, Portland, OR (US); Ravi Motwani, Fremont, CA (US); and Renjie Chen, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 9, 2021, as Appl. No. 17/342,993.
Prior Publication US 2021/0294698 A1, Sep. 23, 2021
Int. Cl. G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H03M 13/45 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1012 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H03M 13/458 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells; and
logic coupled to one or more substrates, the logic to:
conduct a hard-read and a soft-read from a memory cell in the plurality of memory cells in response to an initial request from a controller, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information;
send the hard-bit information to the controller;
send the first soft-bit information with the hard-bit information to the controller while withholding at least the second soft-bit information from the controller;
detect a subsequent request from the controller; and
send the second soft-bit information to the controller in response to the subsequent request.