US 12,339,741 B2
Bit efficient memory error correcting coding and decoding scheme
Fabrice Aidan, Ramat HaSharon (IL); and Evgeni Krimer, Haifa (IL)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Apr. 10, 2023, as Appl. No. 18/132,686.
Claims priority of provisional application 63/448,488, filed on Feb. 27, 2023.
Prior Publication US 2024/0289212 A1, Aug. 29, 2024
Int. Cl. G06F 11/10 (2006.01); H03M 13/00 (2006.01); H03M 13/15 (2006.01)
CPC G06F 11/1044 (2013.01) [H03M 13/1515 (2013.01); H03M 13/613 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for encoding data associated with a request access for one or more DRAMs, comprising:
segmenting a number of beats defined for a burst access to the one or more DRAMs into at least a first set of beats and a second set of beats;
defining a first set of error correction code (ECC) for a first set of data associated with the first set of beats; and
defining a second set of ECC for a second set of data associated with the second set of beats;
wherein one of the first set of ECC comprises a first set of symbols, each symbol of the first set being associated with the first set of beats,
wherein one of the second set of ECC comprises a second set of symbols, each symbol of the second set of symbols being associated with the second set of beats, wherein the first set of symbols comprises a different number of symbols than the second set of symbols and an error associated with the second set of ECC is correctable using information of the first set of ECC, and wherein the second set of ECC comprises one or more symbols used for storing metadata, the metadata being associated with a memory tag extension.