US 12,339,738 B2
Method and chip for cyclic code encoding, circuit component, and electronic device
Liang Li, Beijing (CN); Chun Yuan, Shenzhen (CN); Yuchun Lu, Beijing (CN); Lin Ma, Shenzhen (CN); and Yongzhi Liu, Dongguan (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Oct. 18, 2023, as Appl. No. 18/489,276.
Application 18/489,276 is a continuation of application No. PCT/CN2022/084531, filed on Mar. 31, 2022.
Claims priority of application No. 202110420963.7 (CN), filed on Apr. 19, 2021.
Prior Publication US 2024/0045758 A1, Feb. 8, 2024
Int. Cl. G06F 11/08 (2006.01); H03M 13/00 (2006.01); H03M 13/09 (2006.01); H03M 13/11 (2006.01); H03M 13/15 (2006.01); H03M 13/17 (2006.01); H04L 1/00 (2006.01)
CPC G06F 11/085 (2013.01) [H03M 13/11 (2013.01); H03M 13/15 (2013.01); H03M 13/611 (2013.01); H03M 13/6561 (2013.01); H04L 1/0041 (2013.01); H04L 1/0057 (2013.01); H03M 13/09 (2013.01); H03M 13/152 (2013.01); H03M 13/17 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A method comprising:
generating, based on a first symbol sequence related to a first part of K payload symbols of a first cyclic code, a first parity sequence corresponding to the first symbol sequence, wherein K is an integer greater than 1;
generating, based on a second symbol sequence related to a second part of the K payload symbols, a second parity sequence corresponding to the second symbol sequence, wherein the first part is different from the second part; and
generating (N−K) parity symbols based on the first parity sequence and the second parity sequence,
wherein N is an integer greater than K.