US 12,339,723 B2
Controlling operating voltage of a processor
Ryan D. Wells, Folsom, CA (US); Itai Feit, Herzeliya (IL); Doron Rajwan, Rishon Le-Zion (IL); Nadav Shulman, Tel Mond (IL); Zeev Offen, Folsom, CA (US); and Inder M. Sodhi, Folsom, CA (US)
Assigned to Daedalus Prime LLC, Croton-on-Hudson, NY (US)
Filed by Daedalus Prime LLC, Croton-on-Hudson, NY (US)
Filed on Oct. 26, 2023, as Appl. No. 18/384,180.
Application 18/384,180 is a continuation of application No. 17/969,408, filed on Nov. 1, 2022, granted, now 11,822,409.
Application 17/969,408 is a continuation of application No. 17/645,202, filed on Dec. 20, 2021, granted, now 11,507,167, issued on Nov. 22, 2022.
Application 17/645,202 is a continuation of application No. 17/501,580, filed on Oct. 14, 2021, abandoned.
Application 17/501,580 is a continuation of application No. 16/527,150, filed on Jul. 31, 2019, granted, now 11,175,712, issued on Nov. 16, 2021.
Application 16/527,150 is a continuation of application No. 15/966,397, filed on Apr. 30, 2018, granted, now 10,394,300, issued on Aug. 27, 2019.
Application 15/966,397 is a continuation of application No. 15/157,553, filed on May 18, 2016, granted, now 9,996,135, issued on Jun. 12, 2018.
Application 15/157,553 is a continuation of application No. 13/793,037, filed on Mar. 11, 2013, granted, now 9,367,114, issued on Jun. 14, 2016.
Prior Publication US 2024/0192751 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/28 (2006.01); G06F 1/26 (2006.01); G06F 1/3206 (2019.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0897 (2016.01)
CPC G06F 1/28 (2013.01) [G06F 1/266 (2013.01); G06F 1/3206 (2013.01); G06F 1/324 (2013.01); G06F 1/26 (2013.01); G06F 1/3296 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0897 (2013.01); Y02D 10/00 (2018.01)] 13 Claims
OG exemplary drawing
 
1. A multicore processor comprising:
a plurality of cores, wherein each core comprises a processor configured to operate at an independent voltage and frequency level and at least one core of the plurality of cores is coupled to a plurality of levels of cache memory; and
a power control unit coupled to each of the plurality of cores and, responsive to receiving a first request to alter an operating state of a first core of the plurality of cores from a current operating state to a modified operating state, configured to cause an operating frequency and voltage to be updated for the first core by, prior to modifying a frequency level of the first core from a first frequency level associated with the current operating state to a second frequency level associated with the modified operating state, modifying a voltage for the multicore processor from a current voltage to an intermediate voltage that is a voltage sufficient to power up a second core of the plurality of cores from a low power state to an active state, and, after modification of the voltage for the multicore processor to the intermediate voltage has been achieved, modifying the voltage for the multicore processor from the intermediate voltage to a voltage appropriate for operating the first core at the second frequency level associated with the modified operating state and thereafter changing the operating frequency of the first core from the first frequency level to the second frequency level.