US 12,339,719 B2
Power throttling of high performance computing (HPC) platform components
Akkiah Choudary Maddukuri, Austin, TX (US); Timothy M. Lambert, Austin, TX (US); Elie Antoun Jreij, Pflugerville, TX (US); Bhavesh Govindbhai Patel, Austin, TX (US); and Mukund P. Khatri, Austin, TX (US)
Assigned to Dell Products, L.P., Round Rock, TX (US)
Filed by Dell Products, L.P., Round Rock, TX (US)
Filed on Sep. 18, 2023, as Appl. No. 18/468,771.
Application 18/468,771 is a division of application No. 17/502,130, filed on Oct. 15, 2021, granted, now 11,815,967.
Prior Publication US 2024/0004447 A1, Jan. 4, 2024
Int. Cl. G06F 1/26 (2006.01); G06F 1/28 (2006.01); G06F 9/48 (2006.01); G06F 11/30 (2006.01)
CPC G06F 1/26 (2013.01) [G06F 9/4893 (2013.01); G06F 1/28 (2013.01); G06F 11/3062 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A first Baseboard Management Controller (BMC) of an Information Handling System (IHS), the first BMC having program instructions stored thereon that, upon execution, cause the first BMC to:
determine a power consumption contribution of each of a plurality of managed subsystems coupled to a second BMC; and
in response to a power excursion event, throttle one or more of the plurality of managed subsystems, at least in part, based upon the power consumption contributions;
wherein the first BMC is coupled to a host processor of the IHS, wherein the second BMC is decoupled from the host processor, and wherein the first BMC and the second BMC are coupled to each other via at least one of: a Peripheral Component Interconnect Express (PCIe), RMII-Based Transport (RBT), I2C, or Universal Serial Bus (USB) link.