US 12,339,701 B1
Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis
Yi-Xiao Ding, Austin, TX (US); Sheng-En David Lin, Austin, TX (US); Natarajan Viswanathan, Austin, TX (US); and Charles Jay Alpert, Cedar Park, TX (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Jul. 5, 2023, as Appl. No. 18/347,298.
Int. Cl. G06F 1/14 (2006.01); G06F 1/12 (2006.01)
CPC G06F 1/14 (2013.01) [G06F 1/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
one or more processors of a computing machine; and
a computer storage medium storing instructions, which when executed by the one or more processors, cause the computing machine to perform operations comprising:
receiving a clock signal network layout, the clock signal network layout comprising a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments;
creating a plurality of buffering solutions, each buffering solution of the plurality of buffering solutions comprising a plurality of buffers inserted into one or more net segments of the plurality of net segments;
assigning a timing delay value and an area value to each buffering solution of the plurality of buffering solutions;
selecting a buffering solution from the plurality of buffering solutions based on the timing delay value and the area value; and
applying the selected buffering solution into an integrated circuit (IC) design that comprises the clock signal network layout.