US 12,339,699 B2
Memory, control apparatus, clock processing method, and electronic device
Jingwei Cheng, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 13, 2023, as Appl. No. 18/154,208.
Application 18/154,208 is a continuation of application No. PCT/CN2022/109993, filed on Aug. 3, 2022.
Claims priority of application No. 202210806176.0 (CN), filed on Jul. 8, 2022.
Prior Publication US 2024/0012444 A1, Jan. 11, 2024
Int. Cl. G06F 1/08 (2006.01); G06F 1/10 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/10 (2013.01); G11C 7/1066 (2013.01); G11C 7/222 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 29/50012 (2013.01); G11C 2207/2254 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory, comprising a clock processing circuit, the clock processing circuit comprising:
a duty cycle circuit, configured to receive a data clock signal externally generated, and adjust a duty cycle of the data clock signal to output an internal clock signal;
a first clock generation circuit, configured to receive the internal clock signal, and output a first read clock signal based on the internal clock signal; wherein the first read clock signal is a pulse signal;
a second clock generation circuit, configured to generate and output a second read clock signal during existence of the first read clock signal; wherein the second read clock signal has only one level state change edge; and
a selector, configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as a target read clock signal.