| CPC G06F 1/08 (2013.01) [G06F 1/324 (2013.01)] | 18 Claims |
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1. An electronic device comprising:
a clock management unit configured to generate a clock signal;
an intellectual property (IP) device configured to receive the clock signal and perform a task in an active state according to the clock signal;
a first counter configured to count cycles of the clock signal while the IP device is in the active state;
a second counter configured to count cycles of the clock signal regardless of the active state of the IP device; and
a frequency controller configured to control the clock management unit to,
in response to a first count corresponding to a number of the cycles of the clock signal counted by the first counter reaching a first reference count, increase a frequency of the clock signal by a first value inversely proportional to a second count corresponding to a number of the cycles of the clock signal counted by the second counter, and
in response to the second count counted by the second counter reaching a second reference count, decrease the frequency of the clock signal by a second value inversely proportional to the first count.
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