US 12,339,693 B2
Circuit and system for actively discharging a power stage input node during power supply turn-on
Manuel Wiersch, Freising (DE); and Ferdinand Stettner, Dachau (DE)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 17, 2023, as Appl. No. 18/171,006.
Claims priority of provisional application 63/476,501, filed on Dec. 21, 2022.
Prior Publication US 2024/0210982 A1, Jun. 27, 2024
Int. Cl. G05F 3/26 (2006.01); H03K 17/22 (2006.01)
CPC G05F 3/262 (2013.01) [H03K 17/223 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a current mirror including:
a first field-effect transistor (FET) having a first drain, a first gate, and a first source, wherein:
the first source is coupled with a supply voltage; and
the first gate is coupled to the first drain and to a ground through a resistance element;
a second FET having a second source coupled with the supply voltage, a second gate coupled with the first gate and the first drain, and a second drain configured to provide a fast startup signal;
a third FET having a third source coupled with the supply voltage, a third gate coupled with the first gate and the first drain, and a third drain; and
a fourth FET having a fourth drain coupled with the third drain, a fourth gate coupled with the fast startup signal, and a fourth source configured to provide a startup discharge signal to a gate of a discharge transistor;
a first diode connected in series between the second drain and the ground, wherein the first diode is configured to limit the fast startup signal to a first maximum voltage less than a maximum allowed supply voltage; and
a second diode connected in series between the fourth source and the ground, wherein the second diode is configured to limit the startup discharge signal to a second maximum voltage less than the maximum allowed supply voltage.