US 12,339,632 B2
Training method for semiconductor process prediction model, semiconductor process prediction device, and semiconductor process prediction method
Chia-Wei Chen, Chiayi (TW); Ching-Pei Lin, Hsinchu County (TW); Chung-Yi Chiu, Tainan (TW); Te-Hsuan Chen, Tainan (TW); Ming-Wei Chen, Tainan (TW); and Hsiao-Ying Yang, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsinchu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsinchu (TW)
Filed on Mar. 15, 2022, as Appl. No. 17/695,255.
Claims priority of application No. 202210070302.0 (CN), filed on Jan. 21, 2022.
Prior Publication US 2023/0236553 A1, Jul. 27, 2023
Int. Cl. G05B 13/04 (2006.01); H01L 21/66 (2006.01)
CPC G05B 13/048 (2013.01) [H01L 22/12 (2013.01); H01L 22/14 (2013.01)] 13 Claims
OG exemplary drawing
 
6. A semiconductor process prediction device, comprises:
a process data receiving unit, configured to obtain a plurality of process data of a processing wafer on which a semiconductor process is performed;
a determination unit, configured to determine whether the processing wafer has at least one physical defect according to the process data, wherein if the processing wafer has the at least one physical defect, the processing wafer is a first wafer with the physical defect;
if the processing wafer does not have the at least one physical defect, the processing wafer is a second wafer without the physical defect; and
a semiconductor process prediction model, configured to perform a prediction to predict an electrical measurement data of the second wafer without the physical defect only, wherein the semiconductor process prediction model does not perform the prediction to predict the electrical measurement data of the first wafer with the physical defect.